Kees Goossens, Full Professor in Real-Time Embedded Systems

Kees Goossens, Full Professor in Real-Time Embedded Systems #

  • Fully-functional first-time-right ASIC of a three-core CompSOC platform with Aethereal network on chip and Coarse Grain Reconfigurable Array (CGRA). CompSOC multicore ASIC with Aethereal network on chip CompSOC multicore ASIC test setup

  • My TUE web page.

  • The CompSOC lab web page.

  • My Google scholar page

  • We released a new Version 3.1 of DRAMPower, the Open-Source DRAM Power and Energy Estimation Tool.
    The DRAMPower tool performs DRAM command trace analysis based on memory state transitions and hence, avoids cycle-by-cycle evaluation, thus speeding up simulations. The tool supports all basic DRAM memory operations including read, write, refresh, activate, precharge and auto-precharge, besides active and precharged power-down and self-refresh modes. The tool has also been extended to support power estimation of dual-rank DIMMs including IO and Termination power. This feature also enables power estimation of multiple 3D-stacked Wide IO DRAM dies (equivalent to multiple ranks). Finally, the tool also supports variation-aware power estimation, for a selection of DDR3 memories manufactured at 50nm process technology, based on the Monte-Carlo analysis presented in our DAC'13 article. Check it out now at www.drampower.info.

  • Some guidelines (v2.3) for documents, etc.

  • Poes.

Contact #

Kees Goossens
Electronic Systems group
Electrical Engineering faculty Eindhoven University of Technology (TU/e)
Room 4.133, Flux Building
Groene Loper 19, Eindhoven
The Netherlands

Email: k.g.w.goossens@tue.nl
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Postal address:

Technische Universiteit Eindhoven
Faculty of Electrical Engineering
Postbus 513
5600 MB Eindhoven